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This is my ARM assembly SHA1 implementation for GIT. It is approximately 50% faster than the generic C version. On an XScale processor running at 400MHz: generic C version: 9.8 MB/s my version: 14.5 MB/s It's not that I expect a lot of big GIT users on ARM, but I stillknow about one important ARM user that might benefit from it, and writing that code was fun. I also reworked the makefile a bit so any optimized SHA1 implementations is used regardless of whether NO_OPENSSL is defined or not. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Junio C Hamano <junkio@cox.net>
184 lines
3.5 KiB
ArmAsm
184 lines
3.5 KiB
ArmAsm
/*
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* SHA transform optimized for ARM
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*
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* Copyright: (C) 2005 by Nicolas Pitre <nico@cam.org>
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* Created: September 17, 2005
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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.text
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.globl sha_transform
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/*
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* void sha_transform(uint32_t *hash, const unsigned char *data, uint32_t *W);
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*
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* note: the "data" pointer may be unaligned.
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*/
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sha_transform:
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stmfd sp!, {r4 - r8, lr}
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@ for (i = 0; i < 16; i++)
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@ W[i] = ntohl(((uint32_t *)data)[i]); */
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#ifdef __ARMEB__
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mov r4, r0
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mov r0, r2
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mov r2, #64
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bl memcpy
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mov r2, r0
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mov r0, r4
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#else
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mov r3, r2
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mov lr, #16
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1: ldrb r4, [r1], #1
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ldrb r5, [r1], #1
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ldrb r6, [r1], #1
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ldrb r7, [r1], #1
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subs lr, lr, #1
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orr r5, r5, r4, lsl #8
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orr r6, r6, r5, lsl #8
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orr r7, r7, r6, lsl #8
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str r7, [r3], #4
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bne 1b
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#endif
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@ for (i = 0; i < 64; i++)
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@ W[i+16] = ror(W[i+13] ^ W[i+8] ^ W[i+2] ^ W[i], 31);
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sub r3, r2, #4
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mov lr, #64
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2: ldr r4, [r3, #4]!
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subs lr, lr, #1
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ldr r5, [r3, #8]
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ldr r6, [r3, #32]
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ldr r7, [r3, #52]
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eor r4, r4, r5
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eor r4, r4, r6
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eor r4, r4, r7
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mov r4, r4, ror #31
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str r4, [r3, #64]
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bne 2b
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/*
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* The SHA functions are:
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*
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* f1(B,C,D) = (D ^ (B & (C ^ D)))
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* f2(B,C,D) = (B ^ C ^ D)
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* f3(B,C,D) = ((B & C) | (D & (B | C)))
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*
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* Then the sub-blocks are processed as follows:
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*
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* A' = ror(A, 27) + f(B,C,D) + E + K + *W++
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* B' = A
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* C' = ror(B, 2)
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* D' = C
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* E' = D
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*
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* We therefore unroll each loop 5 times to avoid register shuffling.
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* Also the ror for C (and also D and E which are successivelyderived
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* from it) is applied in place to cut on an additional mov insn for
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* each round.
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*/
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.macro sha_f1, A, B, C, D, E
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ldr r3, [r2], #4
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eor ip, \C, \D
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add \E, r1, \E, ror #2
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and ip, \B, ip, ror #2
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add \E, \E, \A, ror #27
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eor ip, ip, \D, ror #2
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add \E, \E, r3
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add \E, \E, ip
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.endm
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.macro sha_f2, A, B, C, D, E
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ldr r3, [r2], #4
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add \E, r1, \E, ror #2
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eor ip, \B, \C, ror #2
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add \E, \E, \A, ror #27
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eor ip, ip, \D, ror #2
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add \E, \E, r3
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add \E, \E, ip
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.endm
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.macro sha_f3, A, B, C, D, E
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ldr r3, [r2], #4
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add \E, r1, \E, ror #2
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orr ip, \B, \C, ror #2
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add \E, \E, \A, ror #27
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and ip, ip, \D, ror #2
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add \E, \E, r3
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and r3, \B, \C, ror #2
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orr ip, ip, r3
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add \E, \E, ip
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.endm
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ldmia r0, {r4 - r8}
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mov lr, #4
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ldr r1, .L_sha_K + 0
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/* adjust initial values */
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mov r6, r6, ror #30
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mov r7, r7, ror #30
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mov r8, r8, ror #30
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3: subs lr, lr, #1
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sha_f1 r4, r5, r6, r7, r8
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sha_f1 r8, r4, r5, r6, r7
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sha_f1 r7, r8, r4, r5, r6
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sha_f1 r6, r7, r8, r4, r5
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sha_f1 r5, r6, r7, r8, r4
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bne 3b
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ldr r1, .L_sha_K + 4
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mov lr, #4
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4: subs lr, lr, #1
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sha_f2 r4, r5, r6, r7, r8
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sha_f2 r8, r4, r5, r6, r7
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sha_f2 r7, r8, r4, r5, r6
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sha_f2 r6, r7, r8, r4, r5
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sha_f2 r5, r6, r7, r8, r4
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bne 4b
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ldr r1, .L_sha_K + 8
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mov lr, #4
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5: subs lr, lr, #1
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sha_f3 r4, r5, r6, r7, r8
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sha_f3 r8, r4, r5, r6, r7
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sha_f3 r7, r8, r4, r5, r6
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sha_f3 r6, r7, r8, r4, r5
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sha_f3 r5, r6, r7, r8, r4
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bne 5b
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ldr r1, .L_sha_K + 12
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mov lr, #4
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6: subs lr, lr, #1
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sha_f2 r4, r5, r6, r7, r8
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sha_f2 r8, r4, r5, r6, r7
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sha_f2 r7, r8, r4, r5, r6
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sha_f2 r6, r7, r8, r4, r5
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sha_f2 r5, r6, r7, r8, r4
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bne 6b
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ldmia r0, {r1, r2, r3, ip, lr}
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add r4, r1, r4
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add r5, r2, r5
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add r6, r3, r6, ror #2
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add r7, ip, r7, ror #2
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add r8, lr, r8, ror #2
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stmia r0, {r4 - r8}
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ldmfd sp!, {r4 - r8, pc}
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.L_sha_K:
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.word 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6
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